The present invention relates to a system and a method of manufacturing integrated circuits on semiconductor substrates. More specifically, the present invention relates to a system and manufacturing method which improves control of electrical thickness and interface charge density of insulating thin films.
In the semiconductor industry, there is a continuing trend toward manufacturing integrated circuits with a greater number of layers and with higher device densities. To achieve these high densities there have been, and continue to be, efforts towards reducing the thickness of layers, improving the uniformity of layers, reducing the thickness of devices and scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish higher device packing densities, thinner layers, more uniform layers, smaller feature sizes, and smaller separations between features are required. This can include the thickness of gate oxide materials, (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxides and high K materials such as ZrO2 and HfO2 and metal silicates of Hf, Zr, La, etc.), interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and in a substrate that ultimately forms the complete integrated circuit. This layering process can create electrically active regions in and on the semiconductor wafer surface. Insulation and conductivity between such electrically active regions can be important to reliable operation of such integrated circuits. Thus, controlling the width, thickness and/or uniformity of layers created during the layering process can be important to the reliable operation of such integrated circuits. Insulation and conductivity between electrically active regions is important in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor devices.
An exemplary MOSFET device 100 is illustrated in Prior Art. FIG. 1. The exemplary MOSFET device 100 illustrated includes a gate 104 separated from a substrate 110 by a gate oxide 102. The MOSFET includes a source 106 and a drain 108. The thickness of the gate oxide 102 can be important to reliable operation of the MOSFET 100, and thus, manufacturing the gate oxide 102 to precise measurements facilitates increasing MOSFET reliability.
The gate oxide layer 102 functions as an insulating layer. The gate oxide layer 102 can be the smallest feature of a device. Reducing the thickness of the gate oxide layer 102 can contribute to increasing the switching speed of a transistor. But reducing the thickness of the gate oxide layer 102 can lead to problems associated with breakdown and reliability of gate oxides. Thus, precisely monitoring and controlling properties of the gate oxide layer 102 including, but not limited to, thickness and uniformity, are important to facilitating reliable operation of the MOSFET 100. For example, the ability to store data, to retain data, to be erased, to be reprogrammed and to operate in desired electrical and temperature ranges can be affected by the thickness and/or uniformity of the gate oxide layer 102.
In stacked gate oxide films, the gate oxide is comprised of at least two layers but it is to be appreciated that it may be formed from two, three or more layers. The gate oxide is a very thin film, and thus precisely and uniformly forming sublayers having even smaller thickness than the gate oxide film is extremely difficult. The requirement of small features with close spacing between adjacent features in MOSFET devices requires sophisticated manufacturing techniques including precise control of gate oxide layer formation. Furthermore, precise control of layers employed in fabricating stacked gate oxides similarly requires precise control. Fabricating a MOSFET device using such sophisticated techniques may involve a series of steps including the formation of layers/structures by chemical vapor deposition (CVD), rapid thermal oxidation, metal organic CVD (MOCVD), atomic layer CVD (ALCVD), pulsed laser deposition (PLD), thermal oxide growth and other deposition processes. Difficulties in forming a gate oxide layer with precise thickness and/or uniformity have limited the effectiveness and/or properties of MOSFET devices manufactured by conventional techniques.
Measurement of the gate oxide is crucial to maintaining precision and/or uniformity of MOSFET devices. One method of measuring the gate oxide utilizes a corona discharge technique. A corona discharge technique is, a contactless electrical technique for measuring insulating layer thickness of oxides, nitrides, stacks of oxides and/or nitrides, or any other dielectric less than about 300 xc3x85 on a semiconductor substrate. Further, corona discharge is a capacitance-voltage technique for measuring insulating layer thickness on a semiconductor substrate that corrects for the presence of non-zero accumulation bandbending effects (accumulation capacitance) in the substrate, and wherein the need is reduced to bias the oxide-silicon structure strongly into accumulation. A further feature of a corona discharge technique is to provide a measure of the interface charge density of insulating layers on semiconductor substrates, with the insulating layers having thicknesses as low as 10-20 xc3x85, as well as providing a measure of contaminants in the insulating layers.
An exemplary apparatus for making accurate thickness and interface charge density measurements on insulating layers using a corona discharge technique is illustrated in FIG. 2. According to one exemplary corona discharge measurement, a corona discharge source 120 repetitively deposits a calibrated fixed charge density 130 on a surface of a thin oxide layer 140 residing on or over a silicon substrate 150. The resultant change in oxide surface potential 160 for each charge deposition 130 is measured, for example, with a vibrating probe. The change in oxide surface potential 160 is due to the sum of the change in voltage across the oxide layer 170 plus the change in silicon bandbending 180 due to the presence of non-infinite accumulation capacitance in said substrate. The change in oxide surface potential 160 can be utilized to determine electrical thickness (Tox), interface charge density (Dit), total oxide charge (Qtot), flat band voltage (Vfb), onset of oxide tunneling (Etunnel), and various other parameters as will be known by one of ordinary skill in the art.
Due to the extremely fine structures that are fabricated on a MOSFET device, controlling the electrical thickness and other parameters of gate oxide layers employed to form a stacked gate oxide are significant factors in achieving desired critical dimensions and operating properties and thus in manufacturing a reliable MOSFET device. The more precisely the gate oxide can be formed, the more precisely critical dimensions may be achieved, with a corresponding increase in MOSFET device reliability. Conventionally, due to non-uniform and uncontrolled gate oxide layer formation and inaccurate gate oxide layer formation monitoring techniques, a thickness of gate oxide may be formed greater or lesser than the thickness desired.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a corona discharge measurement technique which measures dielectric electrical thickness and associated dielectric-silicon interface charge density of a thin film (e.g., on the order of 200 xc3x85 or less) to control a process of forming the thin film on a substrate.
According to one exemplary aspect of the present invention, a corona discharge measurement technique generally comprises a corona discharge source repetitively depositing a calibrated fixed charge density on the surface of the dielectric. The resultant change in dielectric surface potential for each charge deposition is measured. The resultant change in dielectric surface potential can then be processed to determine the dielectric electrical thickness (Tox) value being sought. The corona discharge measurement can also be used to determine the interface charge density (Dit), total oxide charge (Qtot), flat band voltage (Vfb), onset of oxide tunneling (Etunnel), and various other parameters of the thin film which are also valuable in determining acceptability of the thin film.
The present invention is directed to a system that facilitates control of a thin film formation process involved in semiconductor manufacturing. By utilizing a corona discharge technique for measuring a thin film (e.g., oxide, nitride) formed on a silicon substrate, measured thin film data is fed back to control the formation process. By controlling the thin film formation process with the use of thin film measurement feedback via a corona discharge technique, superior electrical thickness control can be achieved, thereby facilitating the desired performance and functionality of semiconductor devices which comprise the thin film.
An exemplary system may employ one or more process parameters (e.g., temperature, pressure) which govern the formation of the thin film. A thin film formation system is arranged to control the one or more process parameters utilized in the formation of the dielectric thin film on the substrate. A corona discharge measurement system is implemented to measure the thin film formed on the substrate, thereby defining measured thin film data (e.g., electrical thickness, interface charge density). A processor, operatively coupled to the thin film formation system and the corona discharge measurement system, determines whether the one or more process parameters require adjustment based on an analysis of the measured thin film data and target thin film data. A trained neural network, for example, is employed to determine an appropriate adjustment to the one or more process parameters. The adjustment of the one or more process parameters is further implemented by the thin film formation system via feedback from the processor, such that subsequent thin films may be formed utilizing the adjustment.
The present invention is also directed to a method for controlling a thin film formation process utilizing a corona discharge measurement technique. An exemplary method comprises forming a thin film on a substrate based on one or more thin film formation process parameters (e.g., temperature, pressure). The thin film is measured using a corona discharge measurement technique, thereby defining measured thin film data. The measured thin film data and a target thin film data set are analyzed via a processor, and an adjustment to the one or more thin film formation process parameters is determined. The adjustment to the one or more thin film formation process parameters is subsequently performed via the thin film formation system.